To provide reduced power consumption in the dynamic random access memory (DRAM) devices for the mobile market, various low power double data rate (LPDDR) DRAM standards have evolved in which the DRAM may vary the signaling voltage and data rate used to transmit data to a receiving device such as a system-on-a-chip (SOC). A communication channel extends between the SOC and the DRAM over which each bit is transmitted as either a binary high (logic one) symbol or a binary low (logic zero) symbol over the symbol interval. At higher data rates (e.g., 1-10 Giga-bits per second), the channel capacitance causes high-frequency attenuation on transmitted data, and the signal transition expands to adjacent symbol intervals. The resulting inter-symbol interference (ISI) limits the achievable data rates.
To successfully transmit high-speed data, preemphasis techniques have been developed that increase the high-frequency gain for the data transmitter. One way to provide the desired increased high-frequency gain is unit-interval-based (UI-based, referring to the symbol interval as having a unit length) preemphasis. In UI-based preemphasis, a register stores the previous bit state (e.g., logic zero or logic one) to enable the transmitter to have a lower output impedance for a unit interval after a transition (both zero-to-one and one-to-zero). The register requires a high-frequency clock that consumes power and adds to routing complications. As integrated circuit chips are often deployed in mobile devices, power savings has become a focus of interest. Die-to-die interfaces consume power, making it desirable to save power at die-to-die interfaces when possible while providing high signal integrity.
Depending upon the LPDDR protocol, a DRAM may present either a terminated or a non-terminated load to the transmitting device such as an SOC. Although the use of a non-terminated load saves power, such a load is not matched to the characteristic impedance of the channel such that each the data transitions (rising and falling edges) transmitted from the data transmitter to the DRAM may be reflected back to the data transmitter. Moreover, even if a DRAM is presenting a terminated load, it may be included within a bank or group of DRAMs that are not presenting a terminated load such that these additional non-terminated loads cause reflections. Depending upon the nature of the non-terminated load and the electrical distance of the channel, the transmission of a logic one following a logic zero (the transmission of a rising edge for a current bit) may be reflected back as a falling edge during the transmission of a subsequent bit. If the subsequent bit is also a binary one, it may be interpreted as a logical zero by the DRAM due to this interference. Similarly, a binary transition from a one to zero for a current bit may be reflected back as a rising edge during the transmission of the subsequent bit. If the subsequent bit is also a binary zero, it may be interpreted as a binary one by the DRAM due to this interference.
To fight this interference due to reflections from non-terminated loads, the preemphasis should extend beyond a unit interval. But such extended preemphasis is problematic during the transmission of alternating ones and zeros. For example, the preemphasis for a binary one transmission (if extended beyond the unit interval) would then interfere with the transmission of a subsequent binary zero bit.
Accordingly, there is a need in the art for improved lower-power pre-emphasis techniques that address the problems caused by non-terminated loads.